Configurable architecture for virtual socket client to an on-chip bus interface block

ABSTRACT

An interface block provides an interface between an internal bus of an integrated circuit and a socket of a logic block. The interface block includes a synchronization module that performs any needed synchronization between a clock domain of the internal bus and a clock domain of the socket of the logic block. A translation module provides translation of block encoding of the data for data transferred between the internal bus and the socket of the logic block. A queue module buffers data flowing between the internal bus and the socket of the logic block. A driver module handles low level and electrical drive specifications of the internal bus.

BACKGROUND

The present invention concerns the interface between two busses andpertains specifically to a configurable architecture for virtual socketclient to an on-chip bus interface block.

Within an integrated circuit, it is sometimes necessary to provide aninterface between a port of a specialized logic block and an on-chipbus. For example the specialized logic block is proprietary to aparticular vendor.

It is difficult and time consuming to design an efficient interfacebetween a port of a specialized logic block and an on-chip bus. Further,any variation in the configuration requirements of the interface canrequire a complete redesign of the interface.

Modifying a specialized logic block may introduce errors and requiresextensive internal knowledge and re-verification time. Efficient blockre-use needs flexible glue logic to connect blocks with little or nomodifications

SUMMARY OF THE INVENTION

In accordance with the preferred embodiment of the present invention, aninterface block provides an interface between an internal bus of anintegrated circuit and a socket of a logic block. The interface blockincludes a synchronization module that performs any neededsynchronization between a clock domain of the internal bus and a clockdomain of the socket of the logic block. A translation module providestranslation of block encoding of the data for data transferred betweenthe internal bus and the socket of the logic block. A queue modulebuffers data flowing between the internal bus and the socket of thelogic block. A driver module handles low level and electrical drivespecifications of the internal bus.

In one embodiment of the present invention, a plurality of buffers isused to pipeline the interface block. For example, a first buffer islocated between the synchronization module and the translation module, asecond buffer is located between the translation module and the queuemodule, and a third buffer is located between the queue module and thedriver module.

Each of the modules can be individually customized as needed. Forexample, the synchronization module can be implemented as a nullsynchronization block where no synchronization is required between clockdomains, as a ratio synchronization block where the clock domain of theinternal bus is related to the clock domain of the socket of the logicblock by a fixed multiplier ratio, or as a full synchronization blockwhere there is no phase relationship between the clock domain of theinternal bus and the clock domain of the socket of the logic block.

Customization of interface blocks enables the interface block to becompatible with a variety of different proprietary logic blocks andon-chip busses, as well as to accommodate system design goals.Modularity of the interface block enables rapid assembly while stillbeing tuned for a particular application. These features make thisarchitecture especially suited for rapid, system-on-chip implementationsbecause of the inherent isolation of a specialized logic block and theelectrical bus protocol in a rapidly configurable system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that illustrates logic blocks within anintegrated circuit connected to an on-chip bus where a specialty logicblock is connected to the on-chip bus through an interface.

FIG. 1, FIG. 2, FIG. 3, FIG. 4 and FIG. 5 are block diagrams thatillustrate the architecture used for the interface shown in FIG. 2 inaccordance with various preferred embodiments of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows an integrated circuit 200 that includes an on-chip bus 15.Attached to on-chip bus 15 are a logic block 201 and a logic block 202.A specialized logic block 10 is connected to on-chip bus 15 through aninterface block 19. On-chip bus 15 operates, for example, in accordancewith the HP On-chip bus protocol, developed by Hewlett-Packard Company.Alternatively, on-chip bus 15 can operate in accordance with anotheron-chip bus protocol, such as the Motorola M-bus protocol or the ArmAMBA bus protocol. Specialized logic block 10 is, for example aproprietary logic block that has a socket that requires interface block19 for compatibility with on-chip bus 15. For example, specialized logicblock is a logic block such as a Peripheral Component Interconnect (PCI)interface block, a memory controller, a digital signal processor or anapplication specific processor. For example, the block protocol used byspecialized logic block 10 is a common block interface such as Sand CoreInterface, a specific bus protocol (such as M-Bus protocol, or AMBAclient protocol) or a virtual client protocol (such as HP-clientinterface, or Virtual Client Interface)

FIG. 2 shows a configurable architecture for interface block 19. Theconfigurable architecture includes four functional stages. Eachfunctional stage is modular and can be individually configured withoutgrossly affecting neighboring stages.

For example, as shown in FIG. 2, a first stage is implemented as asynchronization block 11. Synchronization block 11 synchronizes databetween the clock domain of logic block 10 and the clock domain ofon-chip bus 15. Synchronization block 11 communicates with specializedlogic block 10 utilizing a virtual socket interface protocol via controlinformation on control lines 20 and data on data lines 25.

The second stage of the configurable architecture for interface block 19is implemented as a translation block 12. Synchronization block 11 andtranslation block 12 exchange control signals synchronized to the clockdomain of on-chip bus 15 via control lines 21 and exchange data signalssynchronized to the clock domain of on-chip bus 15 via data lines 26.Translation block 12 converts the block encoding used by the virtualsocket interface protocol of specialized logic block 10 to the blockencoding used by the protocol implemented on on-chip bus 15. Logicwithin translation block 12 transforms requests used by the virtualsocket interface protocol to equivalent bus requests for the protocolimplemented on on-chip bus 15.

The third stage of the configurable architecture for interface block 19is implemented as a queue block 13. Translation block 12 and queue block13 exchange control signals via control lines 22 and data signals viadata lines 27. Queue block 13 buffers control signals and data signalsso that information from both logic block 10 and on-chip bus 15 can flowindependently.

The fourth stage of the configurable architecture for interface block 19is implemented as a driver block 14. Queue block 13 and driver block 14exchange control signals via control lines 23 and data signals via datalines 28. Driver block 14 generates low-level electrical drive andreceive specification of on-chip bus 15. Driver block 14 and on-chip bus15 exchange control signals via control lines 24 and data signals viadata lines 29.

In an alternative embodiment of interface block 19, the stages can beregistered to allow pipelined access through interface block 19. Thisallows operation at higher clock frequencies.

For example, as shown in FIG. 3, a first stage is implemented as asynchronization block 31. Synchronization block 31 synchronizes databetween the clock domain of logic block 10 and the clock domain ofon-chip bus 15. Synchronization block 31 communicates with specializedlogic block 10 utilizing a virtual socket interface protocol via controlinformation on control lines 40 and data on data lines 45.

The second stage of the configurable architecture for interface block 19is implemented as a translation block 32. A clocked buffer 36 receivesand transmits control signals from/to synchronization block 31 viacontrol lines 41 and receives and transmits data signals from/tosynchronization block 31 via data lines 46. Clocked buffer 36 receivesand transmits control signals from/to translation block 32 via controllines 51 and receives and transmits data signals from/to translationblock 32 via data lines 56. Translation block 32 converts the blockencoding used by the virtual socket interface protocol of specializedlogic block 10 to the block encoding used by the protocol implemented onon-chip bus 15. Logic within translation block 32 transforms requestsused by the virtual socket interface protocol to equivalent bus requestsfor the protocol implemented on on-chip bus 15.

The third stage of the configurable architecture for interface block 19is implemented as a queue block 33. A clocked buffer 37 receives andtransmits control signals from/to translation block 32 via control lines42 and receives and transmits data signals from/to translation block 32via data lines 47. Clocked buffer 37 receives and transmits controlsignals from/to queue block 33 via control lines 52 and receives andtransmits data signals from/to queue block 33 via data lines 57. Queueblock 33 buffers control signals and data signals so that informationfrom both logic block 10 and on-chip bus 15 can flow independently.

The fourth stage of the configurable architecture for interface block 19is implemented as a driver block 34. A clocked buffer 38 receives andtransmits control signals from/to queue block 33 via control lines 43and receives and transmits data signals from/to queue block 33 via datalines 48. Clocked buffer 38 receives and transmits control signalsfrom/to driver block 34 via control lines 53 and receives and transmitsdata signals from/to driver block 34 via data lines 58. Driver block 34generates low-level electrical drive and receive specification ofon-chip bus 15. Driver block 34 and on-chip bus 15 exchange controlsignals via control lines 44 and data signals via data lines 49.

Also, in the preferred embodiments of the present invention, differentstages can be swapped out depending upon the functionality required forinterface block 19. For example, FIG. 4 shows the embodiment shown inFIG. 1, however, synchronization block 11 has been implemented as a nullsynchronization block 61. Null synchronization block 61 is used when nosynchronization is needed between the clock domain of logic block 10 andthe clock domain of on-chip bus 15.

If the clock domain of logic block 10 is related to the clock domain ofon-chip bus 15 by a fixed multiplier ratio, null synchronization block61 can be replaced by a ratio synchronization block 81, as shown in FIG.5. No other changes to interface block 19 are necessary.

If the clock domain of logic block 10 is not phase related to the clockdomain of on-chip bus 15, null synchronization block 61 or ratiosynchronization block 81, can be replaced by a full synchronizationblock 101, as shown in FIG. 6. No other changes to interface block 19are necessary.

The foregoing discussion discloses and describes merely exemplarymethods and embodiments of the present invention. As will be understoodby those familiar with the art, the invention may be embodied in otherspecific forms without departing from the spirit or essentialcharacteristics thereof. Accordingly, the disclosure of the presentinvention is intended to be illustrative, but not limiting, of the scopeof the invention, which is set forth in the following claims.

1.-12. (canceled)
 13. An interface block that provides an interfacebetween an internal bus and a socket of a logic block, the interfaceblock comprising: a plurality of modules located on an integratedcircuit and connected between the internal bus and the socket of thelogic block, wherein each module in the plurality of modules performsonly a single function from a plurality of functions including: a firstfunction for providing any needed synchronization between a clock domainof the internal bus and a clock domain of the socket of the logic block,a second function for providing any required translation of blockencoding of data transferred between the internal bus and the socket ofthe logic block, a third function for providing any buffering of dataflowing between the internal bus and the socket of the logic block, anda fourth function for providing a handling of any low level andelectrical drive specifications of the internal bus.
 14. The interfaceblock of claim 13, wherein one of the plurality of modules is asynchronization module that performs the first function.
 15. Theinterface block of claim 13, wherein one of the plurality of modules isa translation module that performs the second function.
 16. Theinterface block of claim 13, wherein one of the plurality of modules isa queue module that performs the third function.
 17. The interface blockof claim 13, wherein one of the plurality of modules is a driver modulethat performs the fourth function.
 18. The interface block of claim 13,wherein one of the plurality of modules is a synchronization module thatexclusively performs the first function.
 19. The interface block ofclaim 13, wherein one of the plurality of modules is a translationmodule that exclusively performs the second function.
 20. The interfaceblock of claim 13, wherein one of the plurality of modules is a queuemodule that exclusively performs the third function.
 21. The interfaceblock of claim 13, wherein one of the plurality of modules is a drivermodule that exclusively performs the fourth function.
 22. The interfaceblock of claim 13, further comprising: a plurality of buffers, eachbuffer situated between a pair of modules in the plurality of modules,the plurality of buffers used to pipeline the interface block.
 23. Aninterface block that provides an interface between an internal bus and asocket of a logic block, the interface block comprising: a plurality ofmodules located on an integrated circuit, wherein each module in theplurality of modules exclusively performs only a single function from aplurality of functions including: a first function for providing anyneeded synchronization between a clock domain of the internal bus and aclock domain of the socket of the logic block, a second function forproviding any required translation of block encoding of data transferredbetween the internal bus and the socket of the logic block, a thirdfunction for providing any buffering of data flowing between theinternal bus and the socket of the logic block, and a fourth functionfor providing a handling of any low level and electrical drivespecifications of the internal bus.
 24. The interface block of claim 23,wherein one of the plurality of modules is a synchronization module thatexclusively performs the first function.
 25. The interface block ofclaim 23, wherein one of the plurality of modules is a translationmodule that exclusively performs the second function.
 26. The interfaceblock of claim 23, wherein one of the plurality of modules is a queuemodule that exclusively performs the third function.
 27. The interfaceblock of claim 23, wherein one of the plurality of modules is a drivermodule that exclusively performs the fourth function.
 28. The interfaceblock of claim 23, further comprising: a plurality of buffers, eachbuffer situated between a pair of modules in the plurality of modules,the plurality of buffers used to pipeline the interface block.